Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS

This paper presents two novel low cost, double-and-triple-node-upset tolerant latch designs. First, a cost and double-node-upset (DNU) completely (LCDNUT) design is proposed. The mainly comprises storage module (SM) feeding back to 3-input C-element. SM consists of eight input-split inverters. Since the inputs C-element cannot be simultaneously flipped, tolerates any DNU in SM. When single node output are affected, can self-recover from DNU. Second, tolerate triple-node-upset (TNU), by replacing LCDNUT with two-level error-interceptive constructed triple C-elements, TNU (LCTNUT) Simulation results demonstrate robustness proposed latches. Furthermore, due use high-speed transmission path, clock-gating technology fewer transistors, LCTNUT reduces delay-power-area product approximately 99.39 percent has sensitivity process-voltage-and-temperature variation effects, compared currently only design.